AgentIC
Research & Architecture
Runtime: Python 3.10+Architecture: Fail-ClosedValidation: Multi-Corner STA + LECTarget: Sky130 / GF180

Autonomous Text-to-Silicon

A foundational framework for converting natural-language intent into verifiable RTL and physical implementation via structural synthesis loops.

Addressing Paradigm Limitations

AgentIC structurally mitigates two primary failure modes inherent in contemporary LLM-driven EDA workflows.

Fig 1. Silent Regression

LLM pipelines frequently yield false positives against weak assertions. AgentIC enforces deterministic semantic rigor, multi-corner Static Timing Analysis, and Logical Equivalence Checking as non-negotiable exit criteria.

Fig 2. Infinite Churn

Unbounded generative loops reliably diverge. AgentIC implements stateful failure fingerprinting and probabilistic decay boundaries to assert a definitive fail-closed state upon stagnation.

Core Propositions

01 Semantic Preflight

Pre-synthesis structural verification; enforcing exact width resolution and port topological integrity.

02 Finite Execution Bounds

Deterministic limits on generation permutations derived from historical trajectory analysis.

03 Telemetry Reduction

Condensation of verbose EDA execution traces into actionable causal vectors.

04 Implementation Feedback

Closed-loop parameter adjustment informed by localized congestion and WNS deltas.

05 Definitive Signoff

Aggregated validation across power (IR drop), timing (Hold/Setup), and functional equivalence.

06 Hierarchy Scaffolding

Automated modular partitioning dictated by synthesized module interconnect topologies.

State Machine Logic

AgentIC abstains from linear prompt chains. It orchestrates a Directed Acyclic Graph (DAG) with explicit fallback conditions and constraint mutation.

Error Localization

Disambiguates between stimulus faults (Testbench) and logical synthesis faults (RTL), generating discrete summary matrices for contextual repair.

Heuristic Pivoting

Detects timing stagnation (ΔWNS < 0.01ns/epoch). Upon detection, induces structural modifications such as pipeline insertion or target density relaxation.

/* Execution DAG Profile */
STATE_INIT GEN_SPEC SYNTH_RTL
// Syntax / Linter Validation Gate
if (ERR) return MUTATE_RTL
VERIFY_FUNCTIONAL VERIFY_FORMAL
// Assertion Compliance Gate
if (SIM_FAIL) return ANALYZE_TRACE
PLACE_ROUTE PHYSICAL_SIGNOFF
// Performance Convergence Gate
if (WNS_STAGNANT) apply HEURISTIC_RELAXATION
if (DRC_VIOLATION) apply ECO_PATCH
TERMINATE_SUCCESS

Validation Axioms

01 Initialization
Toolchain dependencies and environment assertions validated
02 Synthesis
Syntax, implicit net declarations, and topological sanity verified
03 Dynamic Test
Stimulus execution bounds hit without assertion failures
04 Equivalence
Logical Equivalence Checking (LEC) yields isomorphic graphs
05 Signoff
Zero DRC violations; Setup/Hold timing metrics positive